1. Field of the Invention
The present invention relates to the manufacturing of a CMOS-type integrated circuit.
2. Discussion of the Related Art
In a CMOS-type integrated circuit, various components are formed within properly doped wells. The substrate is of a first conductivity type, for example, an N-type epitaxial layer laid on an N+-type wafer, and wells having a conductivity type opposite to that of the substrate, for example P wells, will more specifically be considered herein in the case where they have a retrograde doping. A retrograde doping well is a well formed by a succession of at least one deep implantation at a high doping level and at least one shallower implantation at a lower concentration. Such structures have the advantage of reducing the necessary thermal processings and limiting the gain of vertical parasitic transistors.
An example of such a structure is illustrated in FIG. 1. A lightly-doped N-type substrate 1 is formed, for example, of an epitaxial layer formed on a heavily-doped N-type silicon wafer. In this substrate is formed a P-type well 2 with a retrograde doping. The periphery of well 2 is defined by an insulating area 4 located at the surface of epitaxial layer 1. This insulating area may be a thick oxide layer resulting from the manufacturing method commonly known as the LOCOS method. However, any other method for forming an insulating peripheral layer, for example, digging and filling up of a trench, may be used. Insulating area 4 will here be called the inter-well insulating area.
In well 2, active areas 8, 9, 10 within which semiconductor components can be formed are defined by thick oxide regions 6, 7, here called intra-well insulating areas. In the drawing, an N-channel MOS type transistor has been shown in each of these regions. As the structure of these components is not the object of the present invention, said components are shown extremely schematically and will not be described in detail, but those skilled in the art will know how to form such components in various ways and with various structure alternatives.
Outside of the perimeter defined by inter-well oxide area 4, are present other elements of a circuit formed in the silicon wafer. These may be other P wells or, as shown, P-channel MOS-type transistors 12 directly formed in epitaxial layer 1 and delimited by other intra-well insulating regions such as region 14. These may also be components formed in N-type wells specifically doped to optimize components to be formed therein.
P-type doped areas 15, conventionally called insulation implantations, formed under each of intra-well insulating areas 6, 7, have also been shown in FIG. 1. Insulation implantations 15 are conventionally formed before insulating regions 6, 7 by implantation at a relatively high doping level, to result in regions having a surface doping level on the order of from 1017 to 1018 atoms/cm3. Insulation implantations 15 aim at avoiding creation of lateral parasitic transistors which would for example have a source corresponding to the drain of a transistor on one side of insulating region 7, a drain corresponding to the source of a transistor on the other side of insulating region 7, and a channel corresponding to the upper portion of the P-type well under the insulating region. Such a parasitic transistor could be started by a voltage applied to a metallization running over insulating region 7. Providing an insulation implantation 15 having a relatively high doping level avoids turning on such a parasitic transistor.
As indicated previously, within wells 2, the choice of a structure of retrograde type enables optimizing many operating parameters of the components, especially reducing the action of vertical parasitic transistors.
However, such retrograde-type wells appear in practice to have a smaller breakdown voltage in reverse biasing, that is, when well P is negatively charged with respect to substrate 1, than conventional wells in which the doping level progressively decreases from the upper surface to the lower area of the well. It is generally considered that this reduced breakdown voltage results from the shape of the periphery of the junction in the area designated by reference 17 and schematically shown in FIG. 1. Instead of a junction having the regular shape designated with reference 18 corresponding to a conventional well, the case of a retrograde doping provides a shape in which the periphery of the P well protrudes in a hump 19 below the surface of the semiconductor wafer. This hump directly results from the way in which a retrograde implantation is performed. Indeed, given that a heavily-doped deep implantation has first been performed before a shallower more lightly-doped implantation, the deep portion in which the implantation has been performed with a higher doping level will have the greatest lateral extent. It can be understood that given this shape of the junction periphery, in reverse biasing, the field lines will tend to curve back and tighten up, which results in a reduction in the breakdown voltage.
Various solutions are known to improve this breakdown voltage. A first solution consists of forming above insulating area 4 a field plate, that is, a conductive area connected to the voltage of the well which takes part in the spreading of the field lines when the device is reverse-biased. This solution has a limited efficiency and does not, by itself sufficiently increase the breakdown voltage. It is generally adopted as a complement to other solutions.
Another solution consists of forming at the periphery of well 2, under insulating layer 4, a more lightly-doped ring, deeper than the well. This solution is efficient but requires implementing additional technological steps. It can thus not be adopted when the manufacturing cost of a component is desired to be lowered.